Semiconductor memory devices are used extensively to store data. Dynamic Random Access Memory (DRAM) is widely used in many applications. Conventional DRAM cells consist of a one-transistor and one-capacitor (1T/1C) structure. As the 1T/1C memory cell feature is being scaled, difficulties arise due to the necessity of maintaining the capacitance values of each memory scale in the scaled architecture.
There is a need in the art for improve DRAM memory that can better retain capacitance values in the cells of a scaled architecture comprising many DRAM memory cells. Because of the rapid growth in the amounts of memory used by modem electronic devices, there is a continuing need to provided improvement in DRAM architecture that allow for a smaller cell size than the currently available 1T/1C memory cell architecture.
Currently existing DRAM memory must be periodically refreshed to maintain the viability of the data stored therein, as the stored charges have a finite lifetime and begin to degrade after a period of time. The charges therefore need to be refreshed to their originally stored values. To do this, the data is first read out and then it is written back into the DRAM. This process must be repeated cyclically after each passage of a predetermined period of time, and is inefficient, as it is both time consuming and energy inefficient.
Thus, there is a need for DRAM memory that is both space efficient and can be efficiently refreshed.
The present inventions satisfies these needs as well as providing additional features that will become apparent upon reading the specification below with reference to the figures.